The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method and structure for reducing floating body effects in metal oxide semiconductor field effect transistor (MOSFET) devices, including silicon-on-insulator (SOI) devices.
Demands for increased performance, functionality and manufacturing economy for integrated circuits have resulted in extreme integration density in order to reduce signal propagation time and increase noise immunity, while also increasing the number of circuits and devices that can be formed on a chip or wafer by a single sequence of processes. Scaling of devices to such small sizes has also restricted operating margins and has necessitated an increased uniformity of electrical characteristics of semiconductor devices formed on a chip.
To satisfy this latter criterion, silicon-on-insulator (SOI) wafers have been used to exploit the improved quality of monocrystalline silicon through an active layer thereof formed on an insulator over a bulk silicon “handling” substrate. Similar attributes may be developed in similar structures of other types of semiconductor materials and alloys thereof. The improved quality of the semiconductor material of the active SOI layer allows transistors and other devices to be scaled to extremely small sizes with good uniformity of electrical properties.
Unfortunately, the existence of the insulator layer (also referred to a buried oxide layer, or BOX) which supports the development of the improved quality of semiconductor material also presents a problem known in the art as the “floating body effect” in transistor structures. The floating body effect is specific to transistors formed on substrates having an insulator layer. In particular, the neutral floating body is electrically isolated by source/drain extension and halo regions that form oppositely poled diode junctions at the ends of the transistor conduction channel and floating body, while the gate electrode is insulated from the conduction channel through a dielectric. The insulator layer in the substrate completes insulation of the conduction channel and thus prevents discharge of any charge that may develop in the floating body. Charge injection into the neutral body when the transistor is not conducting develops voltages in the conduction channel in accordance with the source and drain diode characteristics.
The floating body effect is induced by the excess carriers generated by hot electrons near the strongly filed gradient drain region, resulting in the enhancement in the body potential in SOI devices. It induces a threshold voltage reduction, resulting in a kink in output characteristics. The voltage developed due to charge collection in the transistor conduction channel has the effect of altering the switching threshold of the transistor. This effect, in turn, alters the signal timing and signal propagation speed, since any transistor will have a finite slew rate and the rise and fall time of signals is not instantaneous even when the uniformity of threshold voltage is not good crossing a given electric circuit. SOI switching circuits, in particular, suffer from severe dynamic floating body effects such as hysteresis and history effects. The onset of the kink effect in SOI switching circuits strongly depends on operating frequency, and produces Lorentzian-like noise overshoot and harmonic distortion. Soft error issues are also more serious in SOI MOSFET devices.
In order to limit the charge that builds up in the floating body, a body contact may be incorporated into the device. However, this approach adversely affects the density of the device. Alternatively, the diode characteristics of the source and drain may be tailored. For example, floating body charge may be reduced by decreasing the potential barrier between source/drain and body junctions, such as by creating implant defects at the p/n junctions, which is a frequency independent approach. Unfortunately, as opposed to source diode leakage in a switching device, drain diode leakage increases the thermal power dissipated by a circuit, and reduces actual switching current resulting in lower speed.
Accordingly, it would be desirable to be able to reduce floating body effects (in both SOI devices and bulk silicon devices) in a manner that does not result in increased drain leakage current, reduced integrated circuit density, increased thermal power or speed reduction of the circuit.